Features
6
Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Celeron D processor
samples the hardware configuration at reset, on the active-to-inactive transition of
RESET#. For specifications on these options, refer to Table 34.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
6.2
Clock Control and Low Power States
Table 34.
Power-On Configuration Option Signals
,
Configuration Option
Output tristate
Signal1 2
SMI#
Execute BIST
INIT#
In Order Queue pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
APIC Cluster ID (0-3)
Disable bus parking
A7#
A9#
A10#
A[12:11]#
A15#
BR0#
Symmetric agent arbitration ID
RESERVED
A[6:3]#, A8#, A[14:13]#, A[16:35]#
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not be asserted during
RESET#.
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 15 for a visual representation of the processor low
power states.
Datasheet
85
INTEL [ INTEL ]
