Intel® Celeron® Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Figure 2. AGTL Bus Topology in a Uniprocessor Configuration
Processor
Chipset
I/O
I/O
Note: RESET# requires external termination.
2.2
Clock Control and Low Power States
Processors allow the use of Sleep, and Deep Sleep states to reduce power consumption by stopping
the clock to internal sections of the processor, depending on each particular state. See Figure 3 for a
visual representation of the processor low power states.
Figure 3. Stop Clock State Machine
HALT Instruction and
HALT Bus Cycle Generated
1. Normal State
2. Auto HALT Power Down State
BCLK running.
INIT#, BINIT#, INTR,
SMI#, RESET#
Normal execution.
Snoops and interrupts allowed.
STPCLK# Asserted
STPCLK# De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
and Stop-Grant State
entered from
AutoHALT
Snoop Event Occurs
Snoop Event Serviced
3. Stop Grant State
4. HALT/Grant Snoop State
BCLK running.
Snoops and interrupts allowed.
BCLK running.
Service snoops to caches.
SLP#
SLP#
Asserted
De-asserted
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
BCLK
BCLK
Input
Input
Stopped
Restarted
6. Deep Sleep State
BCLK stopped.
No snoops or interrupts allowed.
PCB757a
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide.
14
Datasheet
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