Intel StrataFlash® Wireless Memory (L18)
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status
Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output
drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a
process which takes a minimum amount of time to complete. When RST# has been deasserted, the
device is reset to asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the initial read
access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can
be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, “AC
Characteristics” on page 28 for details about signal-timing.
9.2
Device Commands
Device operations are initiated by writing specific device commands to the Command User
Interface (CUI). See Table 8, “Command Bus Cycles” on page 47.
Several commands are used to modify array data including Word Program and Block Erase
commands. Writing either command to the CUI initiates a sequence of internally-timed functions
that culminate in the completion of the requested task. However, the operation can be aborted by
either asserting RST# or by issuing an appropriate suspend command.
Table 8.
Command Bus Cycles (Sheet 1 of 2)
First Bus Cycle
Second Bus Cycle
Addr1 Data2
Bus
Cycles
Mode
Command
Oper Addr1 Data2 Oper
Read Array
1
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
PnA
PnA
PnA
PnA
X
0xFF
0x90
0x98
0x70
0x50
Read Device Identifier
CFI Query
Read PBA+IA ID
Read PnA+QA QD
Read
Read Status Register
Clear Status Register
Read PnA
SRD
1
0x40/
0x10
Word Program
2
Write
Write
Write
WA
WA
WA
Write WA
Write WA
Write WA
WD
Program
Buffered Program3
> 2
> 2
0xE8
0x80
N - 1
0xD0
Buffered Enhanced Factory Program
(Buffered EFP)4
Erase
Block Erase
2
Write
BA
0x20
Write BA
0xD0
Program/Erase Suspend
Program/Erase Resume
Lock Block
1
1
2
2
2
Write
Write
Write
Write
Write
X
0xB0
0xD0
0x60
0x60
0x60
Suspend
X
BA
BA
BA
Write BA
Write BA
Write BA
0x01
0xD0
0x2F
Block
Locking/
Unlocking
Unlock Block
Lock-down Block
Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
47
INTEL [ INTEL ]
