Intel StrataFlash® Wireless Memory (L18)
Figure 23.
Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
8.3
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power supply current
considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks
produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the device enable
charge-pumps, and internal logic states change at high speed. All of these internal activities
produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive
and inductive loading. Two-line control and correct decoupling capacitor selection suppress
transient voltage peaks.
Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP,
and VCCQ, each power connection should have a 0.1 µF ceramic capacitor connected to a
corresponding ground connection. High-frequency, inherently low-inductance capacitors should be
placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be
placed between power and ground close to the devices. The bulk capacitor is meant to overcome
voltage droop caused by PCB trace inductance.
Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
43
INTEL [ INTEL ]
