Intel StrataFlash® Wireless Memory (L18)
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus. The on-chip Write State
Machine (WSM) manages all block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash memory
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
9.1
Bus Operations
CE#-low and RST#-high enable device read operations. The device internally decodes upper
address inputs to determine the accessed partition. ADV#-low opens the internal address latches.
OE#-low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously flows through
if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising
ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must
be VIL).
Bus cycles to/from the L18 device conform to standard microprocessor bus operations. Table 7
summarizes the bus operations and the logic levels that must be applied to the device’s control
signal inputs.
Table 7.
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
Synchronous
Burst Suspend
V
V
V
V
V
V
X
L
L
L
L
L
L
L
H
X
L
L
H
H
H
L
Deasserted
Driven
Output
Output
Output
IH
IH
IH
IH
IH
IH
Read
Write
Running
Halted
X
L
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
X
Input
1
2
Output Disable
Standby
X
X
X
H
X
X
High-Z
High-Z
High-Z
2
Reset
V
2,3
IL
Notes:
1.
2.
3.
Refer to the Table 8, “Command Bus Cycles” on page 47 for valid DQ[15:0] during a write operation.
X = Don’t Care (H or L).
RST# must be at V ± 0.2 V to meet the maximum specified power-down current.
SS
Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
45
INTEL [ INTEL ]
