Intel StrataFlash® Wireless Memory (L18)
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before
applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN
.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Reset
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active-low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
System designers should guard against spurious writes when VCC voltages are above VLKO
.
Because both WE# and CE# must be asserted for a write operation, deasserting either signal
inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because alteration
of memory contents can only occur after successful completion of a two-step command sequence
(see Section 9.2, “Device Commands” on page 47).
Nbr. Symbol
Parameter
RST# pulse width low
Min
Max
Unit
Notes
P1
P2
P3
t
t
t
100
-
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
PLPH
RST# low to device reset during erase
RST# low to device reset during program
-
-
25
25
-
PLRH
VCCPH
µs
V
Power valid to RST# deassertion (high)
60
CC
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t is < t min, but this is not guaranteed.
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
PLPH
PLPH
If RST# is tied to the V supply, device will not be ready until t
after V ≥ V min.
CC
VCCPH
CC
CC
If RST# is tied to any supply/signal with V
voltage levels, the RST# input voltage must not exceed
CCQ
V
until V ≥ V (min).
CC
CC CC
7.
Reset completes within t
if RST# is asserted while no erase or program operation is executing.
PLPH
April 2005
42
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
INTEL [ INTEL ]
