LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 13. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function1
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
0
CLOS
1 = Clear/Mask Network loopback interrupt.
0 = Enable Network loopback interrupt.
1
2
CNLOOP
CAIS
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
3
4
5
CQRSS
-
Reserved. Set to 1 for normal operation.
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
CDFMO
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
6
7
CESO
CESU
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 14. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit
Name
Function
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
0
TLOS
1 = NLOOP has changed since last clear NLOOP interrupt occurred.
0 = No change in status.
1
2
TNLOOP
TAIS
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
1 = QRSS has changed since last clear QRSS interrupt occurred1.
0 = No change in status.
3
4
5
TQRSS
-
Reserved. Ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
TDFMO
1 = ES overflow status sticky bit2.
0 = No change in status.
6
7
ESOVR
ESUNF
1 = ES underflow status sticky bit2.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
32
Datasheet
INTEL [ INTEL ]
