Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT362
3.0
Register Definitions
The LXT362 contains five read/write and three read-only registers that are accessible in Host mode
via the serial I/O port. Table 7 lists the LXT362 register addresses. Only bits A6 through A1 of the
address byte are valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/
write (R/W) bit. Table 8 identifies the name of each register bit. Table 9 through Table 17 describe
the function of the bits in each register.
Note that upon power-up or reset, all registers are cleared to 0.
Table 7. Register Addresses
Register
Name
Address1, 2
A7 - A1
Abbr
Control #1
Control #2
CR1
CR2
CR3
ICR
x010000
x010001
x010010
x010011
x010100
x010101
x010110
x010111
Control #3
Interrupt Clear
Transition Status
Performance Status
Equalizer Status
Control #4
TSR
PSR
ESR
CR4
1. x = don’t care
2. Address A0 is the read/write (R/W) bit.
Table 8. Register and Bit Summary
Register
Bit
Name
Type
7
6
5
4
3
2
1
0
Control #1
Control #2
Control #3
CR1 R/W
CR2 R/W
CR3 R/W
JASEL1
RESET
JA6HZ
CESU
JASEL0
EPAT1
ENCENB UNIENB
EC4
EC3
EC2
EC1
EPAT0
ETAOS
ENLOOP EALOOP ELLOOP ERLOOP
reserved1
SBIST
EQZMON reserved1
ES64
CAIS
ESCEN
ESJAM
CLOS
Interrupt Clear ICR R/W
Transition
CESO
CDFMO reserved2
CQRSS
TQRSS
CNLOOP
TSR
PSR
ESR
R
R
R
ESUNF
reserved1
LATN7
ESOVR
BIST
TDFMO
DFMO
LATN5
reserved1
reserved1
LATN4
TAIS
AIS
TNLOOP
NLOOP
TLOS
LOS
Status
Performance
Status
QRSS
Equalizer
Status
LATN6
reserved1 reserved1 reserved1 reserved1
Control #4
CR4 R/W reserved1 reserved1 reserved1 reserved1 reserved1 LOS2048 reserved1 reserved1
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
Datasheet
29
INTEL [ INTEL ]
