M10-DATASHEET
2015.05.04
25
PLL Specifications
Unit
Symbol
Parameter
Condition
Min
Typ
Max
(32)
tCONFIGPLL
Time required to reconfigure scan
chains for PLLs
—
—
3.5
—
SCANCLK cycles
fSCANCLK
scanclk frequency
—
—
—
100
MHz
Table 27: PLL Specifications for MAX 10 Single Supply Devices—Preliminary
For V36 package, the PLL specification is based on single supply devices.
Symbol
Parameter
Condition
Max
660
66
Unit
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
ps
mUI
ps
tOUTJITTER_PERIOD_
Dedicated clock output period jitter
(31)
DEDCLK
660
66
tOUTJITTER_CCJ_
Dedicated clock output cycle-to-cycle jitter
(31)
DEDCLK
mUI
Table 28: PLL Specifications for MAX 10 Dual Supply Devices—Preliminary
Symbol
Parameter
Condition
Max
300
30
Unit
ps
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
tOUTJITTER_PERIOD_
Dedicated clock output period jitter
(31)
DEDCLK
mUI
ps
300
30
tOUTJITTER_CCJ_
Dedicated clock output cycle-to-cycle jitter
(31)
DEDCLK
mUI
(32)
With 100 MHz scanclk frequency.
MAX 10 FPGA Device Datasheet
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