M10-DATASHEET
2015.05.04
23
Core Performance Specifications
Core Performance Specifications
Clock Tree Specifications
Table 25: Clock Tree Specifications for MAX 10 Devices—Preliminary
Performance
–I7
Device
Unit
–I6
450
450
450
450
450
450
450
–C7
416
416
416
416
416
416
416
–A7
382
382
382
382
382
382
382
–C8
10M02
10M04
10M08
10M16
10M25
10M40
10M50
416
402
402
402
402
402
402
402
MHz
MHz
MHz
MHz
MHz
MHz
MHz
416
416
416
416
416
416
PLL Specifications
Table 26: PLL Specifications for MAX 10 Devices—Preliminary
VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
Symbol
Parameter
Condition
Min
Typ
—
Max
472.5
325
Unit
(28)
fIN
Input clock frequency
—
—
5
5
MHz
MHz
fINPFD
Phase frequency detector (PFD) input
frequency
—
(29)
fVCO
PLL internal voltage-controlled
oscillator (VCO) operating range
—
600
—
1300
MHz
(28)
(29)
This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
MAX 10 FPGA Device Datasheet
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