M10-DATASHEET
2015.05.04
24
PLL Specifications
Symbol
Parameter
Condition
Min
40
—
Typ
—
Max
60
Unit
%
fINDUTY
Input clock duty cycle
—
FINPFD ≥ 100 MHz
FINPFD < 100 MHz
—
—
0.15
750
UI
tINJITTER_CCJ
Input clock cycle-to-cycle jitter
(30)
—
—
ps
(28)
fOUT_EXT
PLL output frequency for external clock
output
—
—
472.5
MHz
–6 speed grade
–7 speed grade
–8 speed grade
Duty cycle set to 50%
—
—
—
—
45
—
—
—
—
50
—
472.5
450
402.5
55
MHz
MHz
MHz
%
fOUT
PLL output frequency to global clock
tOUTDUTY
tLOCK
Duty cycle for external clock output
Time required to lock from end of
device configuration
1
ms
tDLOCK
Time required to lock dynamically
After switchover,
reconfiguring any non-
post-scale counters or
delays, or when areset is
deasserted
—
—
1
ms
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
10
—
—
—
—
—
—
650
75
ps
mUI
ps
tOUTJITTER_
Regular I/O period jitter
(31)
PERIOD_IO
650
75
tOUTJITTER_CCJ_
Regular I/O cycle-to-cycle jitter
(31)
IO
mUI
ps
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
50
Minimum pulse width on areset signal.
—
—
ns
(30)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than
200 ps.
(31)
Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
MAX 10 FPGA Device Datasheet
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