M10-DATASHEET
2015.05.04
19
Differential SSTL I/O Standards Specifications
VIL(DC) (V)
VIH(DC) (V)
Min Max
VIL(AC) (V)
VIH(AC) (V)
Min Max
VOL (V)
Max
VOH (V)
Min
I/O Standard
IOL (mA)
IOH (mA)
Min
Max
Min
Max
HSTL-18
Class II
—
VREF
0.1
–
–
–
–
–
–
VREF
0.1
+
+
+
+
+
+
—
—
—
—
VREF
0.2
–
–
–
–
–
–
VREF
0.2
+
+
+
+
+
+
—
—
—
0.4
VCCIO
0.4
–
16
–16
HSTL-15
Class I
—
VREF
0.1
VREF
0.1
—
VREF
0.2
VREF
0.2
0.4
0.4
VCCIO
0.4
–
–
8
–8
–16
–8
HSTL-15
Class II
—
VREF
0.1
VREF
0.1
—
VREF
0.2
VREF
0.2
VCCIO
0.4
16
8
HSTL-12
Class I
–0.15
–0.15
—
VREF
0.08
VREF
0.08
VCCIO
0.15
+
+
–0.24
–0.24
—
VREF
0.15
VREF
0.15
VCCIO
0.24
+
+
0.25 ×
VCCIO
0.75 ×
VCCIO
HSTL-12
Class II
VREF
0.08
VREF
0.08
VCCIO
0.15
VREF
0.15
VREF
0.15
VCCIO
0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
14
—
–14
—
HSUL-12
VREF
0.13
VREF
0.13
—
VREF
0.22
VREF
0.22
—
0.1 ×
0.9 ×
VCCIO
VCCIO
Differential SSTL I/O Standards Specifications
Differential SSTL requires a VREF input.
Table 22: Differential SSTL I/O Standards Specifications for MAX 10 Devices—Preliminary
VCCIO (V)
Typ
VSwing(DC) (V)
VX(AC) (V)
VSwing(AC) (V)
I/O Standard
Min
Max
Min
Max(17)
Min
Typ
Max
Min
Max
SSTL-2 Class I, II
2.375
2.5
2.625
0.36
VCCIO VCCIO/2 –
0.2
—
VCCIO/2+
0.2
0.7
VCCIO
SSTL-18 Class I, II
SSTL-15 Class I, II
1.7
1.8
1.5
1.9
0.25
0.2
VCCIO VCCIO/2 –
0.175
—
—
VCCIO/2+
0.175
0.5
VCCIO
1.425
1.575
—
VCCIO/2 –
0.15
VCCIO/2 + 2(VIH(AC)
0.15 – VREF
2(VIL(AC)
VREF
–
)
)
(17)
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
MAX 10 FPGA Device Datasheet
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