M10-DATASHEET
2015.05.04
20
Differential HSTL and HSUL I/O Standards Specifications
VCCIO (V)
VSwing(DC) (V)
VX(AC) (V)
Typ
VSwing(AC) (V)
Min Max
I/O Standard
Min
Typ
Max
Min
Max(17)
Min
Max
SSTL-135
1.283
1.35
1.45
0.18
—
VREF
–
0.5 ×
VREF
+
2(VIH(AC)
2(VIL(AC)
VREF
–
0.135
VCCIO
0.135
– VREF
)
)
Differential HSTL and HSUL I/O Standards Specifications
Differential HSTL requires a VREF input.
Table 23: Differential HSTL and HSUL I/O Standards Specifications for MAX 10 Devices—Preliminary
VCCIO (V)
Typ
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
Min
I/O Standard
Min
Max
Min
Max
Min
Max
Min
Max
HSTL-18 Class
I, II
1.71
1.8
1.89
0.2
—
0.85
—
0.95
0.85
—
0.95
0.4
HSTL-15 Class
I, II
1.425
1.14
1.14
1.5
1.2
1.2
1.575
1.26
1.3
0.2
—
VCCIO
—
0.71
—
0.79
0.71
—
0.79
0.4
0.3
HSTL-12 Class
I, II
0.16
0.26
0.48 ×
VCCIO
0.5 ×
0.52 ×
VCCIO
0.48 ×
VCCIO
0.5 ×
0.52 ×
VCCIO
VCCIO
VCCIO
HSUL-12
0.5 ×
0.5 ×
0.5 ×
0.4 ×
0.5 ×
0.6 ×
0.44
VCCIO
0.12
–
VCCIO VCCIO
0.12
+
VCCIO
VCCIO
VCCIO
(17)
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
MAX 10 FPGA Device Datasheet
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