A10-DATASHEET
2015.12.31
95
Glossary
Term
Definition
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
JTAG Timing Specifications
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
tJPXZ
tJPZX
tJPCO
TDO
Preliminary
Some tables show the designation as “Preliminary”. Preliminary characteristics are created using
simulation results, process data, and other known parameters.
Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual
performance of the device under worst-case silicon process, voltage, and junction temperature conditions.
There are no preliminary designations on finalized tables.
RL
Receiver differential input discrete resistor (external to the Arria 10 device).
Sampling window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly.
The setup and hold times determine the ideal strobe position in the sampling window, as shown:
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
Arria 10 Device Datasheet
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