欢迎访问ic37.com |
会员登录 免费注册
发布采购

10AX057H4F34I3LG 参数 Datasheet PDF下载

10AX057H4F34I3LG图片预览
型号: 10AX057H4F34I3LG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
 浏览型号10AX057H4F34I3LG的Datasheet PDF文件第89页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第90页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第91页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第92页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第94页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第95页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第96页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第97页  
A10-DATASHEET  
2015.12.31  
93  
Programmable IOE Delay  
Programmable IOE Delay  
Table 86: IOE Programmable Delay for Arria 10 Devices—Preliminary  
For the exact values for each setting, use the latest version of the Quartus Prime software.  
Fast Model  
Slow Model  
–I3S  
Available  
Settings  
Minimum  
Offset (114)  
Parameter (113)  
Unit  
Extended  
Industrial  
–I1L  
–I2S  
–E2S  
–E3S  
Input Delay  
Chain Setting  
(IO_IN_DLY_  
CHN)  
64  
16  
0
0
1.829  
1.820  
4.128  
4.764  
5.485  
4.764  
5.485  
ns  
Output Delay  
Chain Setting  
(IO_OUT_  
0.433  
0.430  
0.990  
1.145  
1.326  
1.145  
1.326  
ns  
DLY_CHN)  
(113)  
(114)  
You can set this value in the Quartus Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment  
Name column.  
Minimum offset does not include the intrinsic delay.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
 复制成功!