欢迎访问ic37.com |
会员登录 免费注册
发布采购

10AX057H4F34I3LG 参数 Datasheet PDF下载

10AX057H4F34I3LG图片预览
型号: 10AX057H4F34I3LG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
 浏览型号10AX057H4F34I3LG的Datasheet PDF文件第95页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第96页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第97页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第98页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第100页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第101页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第102页浏览型号10AX057H4F34I3LG的Datasheet PDF文件第103页  
A10-DATASHEET  
2015.12.31  
99  
Document Revision History  
Date  
Version  
Changes  
Added –E2V, –I2V, –E3V, and –I3V speed grades in DSP Block Performance Specifications for Arria 10  
Devices (VCC and VCCP at 0.9 V Typical Value) table.  
Updated Memory Block Performance Specifications for Arria 10 Devices table for VCC and VCCP at 0.9 V  
typical value. Added memory block performance specifications for VCC and VCCP at 0.95 V typical value.  
Removed the "Minimum Resolution with no Missing Codes" column in Internal Temperature Sensing  
Diode Specifications for Arria 10 Devices table.  
Added a link in the Internal Temperature Sensing Diode Specifications section: Transfer Function for  
Internal TSD topic in the Power Management in Arria 10 Devices chapter, Arria 10 Core Fabric and General  
Purpose I/Os Handbook.  
Added descriptions to External Temperature Sensing Diode Specifications for Arria 10 Devices table.  
Updated Internal Voltage Sensor Specifications for Arria 10 Devices table.  
Updated maximum resolution from 12 bits to 8 bits. Removed minimum resolution value.  
Updated maximum integral non-linearity (INL) from 3 LSB to 1 LSB.  
Updated maximum clock frequency from 20 MHz to 11 MHz.  
Added gain error and offset error specifications.  
Removed signal to noise and distortion ratio (SNR) specifications.  
Removed Bipolar input mode specifications.  
Updated "slow clock" to "core clock" in DPA Lock Time Specifications with DPA PLL Calibration Enabled  
diagram.  
Updated the maximum values of the following conditions for Transmitter True Differential I/O Standards -  
fHSDR (data rate) parameter in High-Speed I/O Specifications for Arria 10 Devices table.  
SERDES factor J = 2, uses DDR registers  
SERDES factor J = 1, uses DDR registers  
Added the following tables:  
Memory Standards Supported by the Hard Memory Controller for Arria 10 Devices  
Memory Standards Supported by the Soft Memory Controller for Arria 10 Devices  
Updated minimum TOCTCAL value from 1000 cycles to 2000 cycles in OCT Calibration Block Specifications  
for Arria 10 Devices table.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
 复制成功!