A10-DATASHEET
2015.12.31
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User Watchdog Internal Circuitry Timing Specifications
Parameter
Minimum
250
Maximum
Unit
ns
(111)
tRU_nCONFIG
—
—
(112)
tRU_nRSTIMER
250
ns
Related Information
•
Remote System Upgrade State Machine
Provides more information about configuration reset (RU_CONFIG) signal.
User Watchdog Timer
•
Provides more information about reset_timer (RU_nRSTIMER) signal.
User Watchdog Internal Circuitry Timing Specifications
Table 85: User Watchdog Internal Oscillator Frequency Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Typical
Maximum
Unit
User watchdog internal oscillator frequency
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus Prime Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete
place-and-route.
Related Information
Arria 10 I/O Timing Spreadsheet
Provides the Arria 10 Excel-based I/O timing spreadsheet.
(111)
(112)
This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
Arria 10 Device Datasheet
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