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10AX057H4F34I3LG 参数 Datasheet PDF下载

10AX057H4F34I3LG图片预览
型号: 10AX057H4F34I3LG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
90  
Minimum Configuration Time Estimation  
Minimum Configuration Time Estimation  
Table 83: Minimum Configuration Time Estimation for Arria 10 Devices—Preliminary  
The estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Arria 10 Devices table.  
Active Serial (108)  
Fast Passive Parallel (109)  
Variant  
Product Line  
Width  
DCLK (MHz) Minimum Configuration  
Time (ms)  
Width  
DCLK (MHz) Minimum Configuration Time  
(ms)  
GX 016  
GX 022  
GX 027  
GX 032  
GX 048  
GX 057  
GX 066  
GX 900  
GX 1150  
GT 900  
GT 1150  
4
4
4
4
4
4
4
4
4
4
4
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
204.81  
204.81  
306.48  
306.48  
443.35  
632.08  
632.08  
883.20  
883.20  
883.20  
883.20  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
32  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
25.60  
25.60  
38.31  
38.31  
55.42  
79.01  
79.01  
110.40  
110.40  
110.40  
110.40  
Arria 10 GX  
Arria 10 GT  
(108)  
The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSRmay guarantee the frequency accuracy  
of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal  
oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.  
Arria 10 Device Datasheet  
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Altera Corporation  
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