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10AX057H4F34I3LG 参数 Datasheet PDF下载

10AX057H4F34I3LG图片预览
型号: 10AX057H4F34I3LG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
87  
Initialization  
Symbol  
Parameter  
nCONFIGhigh to first rising edge on DCLK  
nSTATUShigh to first rising edge of DCLK  
DATA[]setup time before rising edge on DCLK  
DATA[]hold time after rising edge on DCLK  
DCLKhigh time  
Minimum  
Maximum  
Unit  
μs  
μs  
ns  
ns  
s
(104)  
tCF2CK  
3,010  
(104)  
tST2CK  
tDSU  
tDH  
10  
5.5  
0
0.45 × 1/fMAX  
0.45 × 1/fMAX  
1/fMAX  
tCH  
tCL  
DCLKlow time  
s
tCLK  
fMAX  
tCD2UM  
tCD2CU  
DCLKperiod  
s
DCLKfrequency  
CONF_DONEhigh to user mode (105)  
125  
830  
MHz  
μs  
175  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLK  
period  
tCD2UMC  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (600 ×  
CLKUSRperiod)  
Related Information  
PS Configuration Timing  
Provides the PS configuration timing waveform.  
Initialization  
Table 81: Initialization Clock Source Option and the Maximum Frequency for Arria 10 Devices—Preliminary  
Initialization Clock Source  
Internal Oscillator  
CLKUSR(106)(107)  
Configuration Scheme  
AS, PS, and FPP  
Maximum Frequency (MHz)  
Minimum Number of Clock Cycles  
12.5  
100  
600  
AS, PS, and FPP  
(104)  
(105)  
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.  
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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