A10-DATASHEET
2015.12.31
50
DPA Lock Time Specifications
Symbol
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SGMII/GbE
protocol
—
—
5
—
—
5
—
—
5
UI
—
DPA (soft
All other
protocols
—
—
50 data
transition
per 208
UI
—
—
50 data
transition
per 208
UI
—
—
50 data
transition
per 208
UI
DPA run length
CDR mode)
Soft CDR
mode
Soft-CDR ppm
tolerance
—
—
—
—
—
—
300
—
—
—
—
300
—
—
—
—
300
ppm
ps
Non DPA
mode
Sampling Window
300
300
300
DPA Lock Time Specifications
Figure 2: DPA Lock Time Specifications with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 core
clock cycles
256 data
transitions
96 core
clock cycles
256 data
transitions
(64)
(65)
(76)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
When you power VCC and VCCP at nominal voltage of 0.90 V.
(64)
(65)
When you power VCC and VCCP at lower voltage of 0.83 V.
Arria 10 Device Datasheet
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