A10-DATASHEET
2015.12.31
49
High-Speed I/O Specifications
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Symbol
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SERDES factor
—
—
1600
—
—
1434
—
—
1250
Mbps
Mbps
Mbps
Mbps
J = 4 to 10 (69)(71)(70)
True Differential I/O
Standards - fHSDRDPA
(data rate)
(72)
(76)
(73)
(72)
(76)
(73)
(72)
(76)
(73)
SERDES factor
J = 3 (69)(71)(70)
—
—
—
—
—
—
—
—
—
—
—
—
(71)
(71)
(71)
SERDES factor
J = 3 to 10
Receiver
(71)
(71)
(71)
(71)
(71)
(71)
SERDES factor J
= 2, uses DDR
registers
fHSDR (data rate)
(without DPA) (68)
(73)
(73)
(73)
SERDES factor J
= 1, uses DDR
registers
—
—
—
—
—
—
Mbps
UI
DPA (FIFO DPA run length
mode)
—
—
10000
—
10000
—
10000
(68)
(69)
Requires package skew compensation with PCB trace length.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design
dependent and requires timing analysis.
(70)
(71)
The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
Pending silicon characterization.
The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity meets the interface requirements.
Not applicable for DIVCLK= 1.
This applies to default pre-emphasis and VOD settings only.
(72)
(73)
(74)
(75)
Arria 10 Device Datasheet
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