IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Registers:
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
7
0
0
0
0
A
X
ACCUMULATOR
7
INDEX REGISTER
PROGRAM COUNTER
STACK POINTER
12
8
7
PCL
PCH
0
12
0
6
0
0
0
0
1
SP
CC
4
0
H
I
N
Z
C
CONDITION CODE REGISTER
CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
Figure 6. Programming Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
STACK
CONDITION CODE
I
1
1
1
REGISTER
N
T
R
E
T
U
R
N
ACCUMULATOR
INDEX REGISTER
E
R
R
U
P
T
DECREASING MEMORY
ADDRESSES
INCREASING MEMORY
ADDRESSES
0
0
0
PCH
PCL
UNSTACK
Figure 7. Interrupt Stacking Order
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