IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
DESCRIPTIO N
SIG NAL NAM E
VDD and VSS
I/O
Source: These two pins provide power to the chip. VDD provides +5 volts (±0.5)
power and VSS is ground.
N/A
(Pow er and G round)
TTL: Input pin that can be used to reset the M PU's internal state by pulling the reset_n
pin low.
RESET_n
(Reset)
I
I
TTL: Input pin that is level and edge sensitive. Can be used to request an interrupt
sequence.
IRQ _n
(Interrupt Request)
TTL w ith slew rate control: O utput pin used to indicate that a next opcode fetch is in
progress. Used only for certain debugging and test system s. Not connected in
norm al operation. O verlaps Data Strobe (DS) signal. This output is capable of driving
one standard TTL load and 50pF.
LI
O
O
O
(Load Instruction)
TTL w ith slew rate control: O utput pin used to transfer data to or from a peripheral
or m em ory. DS occurs anytim e the M PU does a data read or write and during data
transfer to or from internal m em ory. DS is available at fO SC ¸5 when the M PU is not in
the W AIT or STO P m ode. This output is capable of driving one standard TTL load and
DS
(Data Strobe)
130pF.
TTL w ith slew rate control: O utput pin used to indicate the direction of data transfer
from internal m em ory, I/O registers, and external peripheral devices and m em ories.
Indicates to a selected peripheral whether the M PU is to read (RW _n high) or write
(RW _n low) data on the next data strobe. This output is capable of driving one
RW _n
(Read/W rite)
standard TTL load and 130pF.
TTL w ith slew rate control: O utput strobe used to indicate the presence of an
address on the 8-bit m ultiplexed bus. The AS line is used to dem ultiplex the eight
least significant address bits from the data bus. AS is available at fO SC ¸ 5 when the
M PU is not in the W AIT or STO P m odes. This output is capable of driving one
standard TTL load and 130pF.
AS
O
(Address Strobe)
TTL w ith slew rate control: These 16 lines constitute Input/O utput ports A and B.
Each line is individually program m ed to be either an input or output under software
control of the Data Direction Register (DDR) as shown below in Table 1 and Figure 2.
The port I/O is program m ed by writing the corresponding bit in the DDR to a "1" for
output and a "0" for input. In the output m ode the bits are latched and appear on the
corresponding output pins. All the DDR's are initialized to a "0" on reset. The output
port registers are not initialized on reset. Each output is capable of driving one
standard TTL load and 50pF.
PA0-PA7/PB0-PB7
(Input/O utput Lines)
I/O
A8-A12
(High O rder Address
Lines)
TTL w ith slew rate control: These five outputs constitute the higher order non-
m ultiplexed address lines. Each output is capable of driving one standard TTL load
and 130pF.
O
TTL w ith slew rate control: These bi-directional lines constitute the lower order
addresses and data. These lines are m ultiplexed with address present at address
strobe tim e and data present at data strobe tim e. W hen in the data m ode, these lines
are bi-directional, transferring data to and from m em ory and peripheral devices as
indicated by the RW _n pin. As outputs, these lines are capable of driving one
standard TTL load and 130pF.
B0-B7
(Address/Data Bus)
I/O
I
TTL: Input used to control the internal tim er/counter circuitry.
Tim er
TTL O scillator input/output: These pins provide control input for the on-chip clock
oscillator circuits. Either
a crystal or external clock is connected to these pins to
O SC1, O SC2
(System Clock)
provide a system clock. The crystal connection is shown in Figure 3. The O SC1 to
bus transitions for system designs using oscillators slower than 5M Hz is shown in
Figure 4.
The circuit shown in Figure 3 is recom m ended when using
a crystal. An external
I/O
CM O S oscillator is recom m ended when using crystals outside the specified ranges.
To m inim ize output distortion and start-up stabilization tim e, the crystal and
com ponents should be m ounted as close to the input pins as possible.
Crystal
W hen an external clock is used, it should be applied to the O SC1 input with the O SC2
input not connected, as shown in Figure 3.
External Clock
Table 1
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IA211081401-03
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