IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
RESET
I BIT
?
SET
CLEAR
STACK
PC, X, A, CC
I_CC <= 1
SP <= $007F
DDRs <= 0
CLEAR
IRQ_N
REQUEST
LATCH
IRQ_N
Y
IRQ_N
EDGE
CLR IRQ_N LOGIC
TIMER <= $FF
PRESCALER <= $7F
TCR <= $7f
?
N
I <= 1
TCR6=0
Y
TIMER
AND
LOAD PC FROM:
SWI: 1FFC/1FFD
IRQ_N: 1FFA/1FFB
TIMER: 1FF8/1FF9
TIMER WAIT:1FF6/
1FF7
TCR7=1?
PUT 1FFE,1FFF ON
ADDRESS BUS
N
FETCH
INSTRUCTION
IN
RESET
Y
?
RESET_N
PIN = LOW
RESET_N
N
PIN = LOW
IS FETCHED
Y
SWI
INSTRUCTION
PC+1=>PC
AN SWI?
LOAD PC
FROM
1FFE/1FFF
N
EXECUTE ALL
INSTRUCTION
CYCLES
Figure 8. Reset and Interrupt Processing Flowchart
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IA211081401-03
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