IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
External Interrupt:
If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code
register is cleared, the external interrupt occurs. When the interrupt is recognized, the
current state of the machine is pushed onto the stack and the condition code register I-bit
gets set masking further interrupts until the present one is serviced. The program counter is
then loaded with the contents of the interrupt vector, which contains the location of the
interrupt service routine. The contents of $1FFA and $1FFB specify the address for this
service routine. A functional diagram of the external interrupt is shown in Figure 9 and a
mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows
two different treatments of the interrupt line (irq_n) to the processor. The first shows
several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt
line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The
second shows single pulses on the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of the interrupt service. After a
pulse occurs, the next pulse should not occur until an RTI has occurred. The time between
pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes
to complete the service routine including the RTI instruction.
VDD
EXTERNAL
D
C
Q
Q
INTERUPT
REQUEST
INTERRUPT PIN
I BIT (CCR)
R
POWER-ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED
Figure 9. Interrupt Functional Diagram
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