IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
LIST OF TABLES
Table 1. IA186ER LQFP Numeric Pin Listing.............................................................................17
Table 2. IA186ER LQFP Alphabetic Pin Listing .........................................................................18
Table 3. IA188ER LQFP Numeric Pin Listing.............................................................................20
Table 4. IA188ER LQFP Alphabetic Pin Listing.........................................................................21
Table 5. IA186ER PQFP Numeric Pin Listing.............................................................................24
Table 6. IA186ER PQFP Alphabetic Pin Listing .........................................................................25
Table 7. IA188ER PQFP Numeric Pin Listing.............................................................................27
Table 8. IA188ER PQFP Alphabetic Pin Listing .........................................................................28
Table 9. Bus Cycle Types for bhe_n and ad0 ...............................................................................31
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n...................................................................38
Table 11. IA186ER and IA188ER Absolute Maximum Ratings..................................................43
Table 12. IA186ER and IA188ER Thermal Characteristics.........................................................43
Table 13. DC Characteristics Over Industrial Operating Ranges.................................................43
Table 14. Interrupt Types..............................................................................................................51
Table 15. Default Status of PIO Pins at Reset ..............................................................................56
Table 16. Peripheral Control Registers.........................................................................................59
Table 17. Peripheral Control Block Relocation Register..............................................................60
Table 18. Reset Configuration Register........................................................................................60
Table 19. Processor Release Level Register.................................................................................61
Table 20. Power-Save Control Register........................................................................................61
Table 21. Watchdog Timer Control Register................................................................................62
Table 22. Enable Dynamic RAM Refresh Control Register.........................................................63
Table 23. Count for Dynamic RAM Refresh Control Register ....................................................64
Table 24. Memory Partition for Dynamic RAM Refresh Control Register .................................64
Table 25. DMA Control Registers................................................................................................64
Table 26. DMA Transfer Count Registers....................................................................................66
Table 27. DMA Destination Address High Register ....................................................................67
Table 28. DMA Destination Address Low Register.....................................................................67
Table 29. DMA Source Address High Register............................................................................68
Table 30. DMA Source Address Low Register ............................................................................68
Table 31. Internal Memory Chip Select Register .........................................................................68
Table 32. MCS and PCS Auxiliary Register ................................................................................69
Table 33. Midrange Memory Chip Select Register ......................................................................70
Table 34. Peripheral Chip Select Register....................................................................................72
Table 35. Low-Memory Chip Select Register..............................................................................73
Table 36. Upper-Memory Chip Select Register ...........................................................................74
Table 37. Baud Rates ....................................................................................................................75
Table 38. Serial Port Baud Rate Divisor Registers.......................................................................76
Table 39. Serial Port Receive Data Register.................................................................................76
Table 40. Serial Port Transmit Data Register ...............................................................................77
Table 41. Serial Port Status Register ............................................................................................77
IA211110517-02
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