IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
2.2.45 uzi_n/clksel2_n/pio26—Upper Zero Indicate (synchronous
output)/clock select 2 (input, pullup)..............................................................40
2.2.46 vcc—Power Supply (input)..............................................................................40
2.2.47 whb_n (IA186ER)—Write High Byte (synchronous output with
tristate)............................................................................................................41
2.2.48 wlb_n/wb_n—Write Low Byte (IA186ER) (synchronous output with
tristate)/Write Byte (IA188ER) (synchronous output with tristate) ...............41
2.2.49 wr_n—Write Strobe (synchronous output) ....................................................41
2.2.50 x1—Crystal Input (input) ...............................................................................41
2.2.51 x2—Crystal Input (input) ...............................................................................41
2.3 Pins Used by Emulators ..............................................................................................41
Maximum Ratings, Thermal Characteristics, and DC Parameters.......................................43
Device Architecture..............................................................................................................44
4.1 Bus Interface and Control ...........................................................................................44
4.2 Clock and Power Management ...................................................................................46
4.3 System Clocks.............................................................................................................46
4.4 Power-Save Mode .......................................................................................................47
4.5 Initialization and Reset................................................................................................47
4.6 Reset Configuration Register ......................................................................................47
4.7 Chip Selects.................................................................................................................47
4.8 Chip - Select Timing ...................................................................................................47
4.9 Ready- and Wait-State Programming..........................................................................48
4.10 Chip Select Overlap ....................................................................................................48
4.11 Upper Memory Chip Select.........................................................................................49
4.12 Low Memory Chip Select ...........................................................................................49
4.13 Midrange Memory Chip Selects .................................................................................49
4.14 Peripheral Chip Selects ...............................................................................................50
4.15 Refresh Control ...........................................................................................................50
4.16 Interrupt Control..........................................................................................................50
4.16.1 Interrupt Types................................................................................................51
4.17 Timer Control..............................................................................................................52
4.18 Direct Memory Access (DMA)...................................................................................53
4.19 DMA Operation...........................................................................................................53
4.20 DMA Channel Control Registers ................................................................................54
4.21 DMA Priority ..............................................................................................................54
4.22 Asynchronous Serial Port............................................................................................54
4.23 Synchronous Serial Port..............................................................................................55
4.24 Programmable I/O (PIO).............................................................................................55
4.25 Watchdog Timer..........................................................................................................57
4.26 Internal Memory..........................................................................................................58
Peripheral Architecture.........................................................................................................58
5.1 Control and Registers..................................................................................................58
5.1.1 RELREG (0feh)..............................................................................................60
3.
4.
5.
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