IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
2.2.18 int2/inta0_n/pio31—Maskable Interrupt Request 2 (asynchronous
input)/Interrupt Acknowledge 0 (synchronous output) ..................................34
2.2.19 int3/inta1_n/irq—Maskable Interrupt Request 3 (asynchronous
input)/Interrupt Acknowledge 1 (synchronous output)/Interrupt
Request (synchronous output) ........................................................................34
2.2.20 int4/pio30—Maskable Interrupt Request 4 (asynchronous input)..................34
2.2.21 lcs_n/once0_n—Lower Memory Chip Select (synchronous output
with internal pull-up)/ONCE Mode Request (input)......................................35
2.2.22 mcs2_n—mcs0_n (pio24, pio15, pio 14)—Midrange Memory Chip
Selects (synchronous outputs with internal pull-up) ......................................35
2.2.23 mcs3_n/rfsh_n/pio25—Midrange Memory Chip Select (synchronous
output with internal pull-up)/Automatic Refresh (synchronous output) ........35
2.2.24 nmi—Nonmaskable Interrupt (synchronous edge-sensitive input) ................35
2.2.25 pcs3_n–pcs0_n (pio19–pio16)—Peripheral Chip Selects 3–0
(synchronous outputs).....................................................................................36
2.2.26 pcs5_n/a1/pio3—Peripheral Chip Select 5 (synchronous
output)/Latched Address Bit 1 (synchronous output).....................................36
2.2.27 pcs6_n/a2/pio2—Peripheral Chip Select 6 (synchronous
output)/latched Address Bit 2 (synchronous output)......................................36
2.2.28 pio31–pio0—Programmable I/O Pins (asynchronous input/output
open-drain)......................................................................................................37
2.2.29 rd_n—Read strobe (synchronous output with tristate)...................................37
2.2.30 res_n—Reset (asynchronous level-sensitive input)........................................37
2.2.31 rfsh2_n/aden_n (IA188ER)—Refresh 2 (synchronous output with
tristate)/Address Enable (input with internal pull-up)....................................37
2.2.32 rxd/pio28—Receive Data (asynchronous input) ............................................37
2.2.33 s0_n, s1_n (imdis_n), s0_n (sren_n) —Bus Cycle Status (synchronous
outputs with tristate) .......................................................................................38
2.2.34 s6/clksel1_n/pio29—Bus Cycle Status Bit 6 (synchronous
output)/Clock Divide by 2 (input with internal pull-up) ................................38
2.2.35 sclk/pio20 —Serial Clock (synchronous outputs with tristate) ......................39
2.2.36 sdata/pio21 —Serial Data (synchronous inout)..............................................39
2.2.37 sden1/pio23 – sden0/pio22 —Serial Data Enables (synchronous
outputs with tristate) .......................................................................................39
2.2.38 srdy/pio6—Synchronous Ready (synchronous level-sensitive input)............39
2.2.39 tmrin0/pio11—Timer Input 0 (synchronous edge-sensitive input) ................39
2.2.40 tmrin1/pio0—Timer Input 1 (synchronous edge-sensitive input) ..................39
2.2.41 tmrout0/pio10—Timer Output 0 (synchronous output) .................................40
2.2.42 tmrout1/pio1—Timer Output 1 (synchronous output) ...................................40
2.2.43 txd/pio27—Transmit Data (asynchronous output) .........................................40
2.2.44 ucs_n/once1_n—Upper Memory Chip Select (synchronous
output)/ONCE Mode Request 1 (input with internal pull-up)........................40
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