IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 93. Clock Timing
No.
Name
Description
Min
Max
Units
CLKIN Requirements (Times Four Mode)
36
37
38
39
40
tCKIN
tCLCK
tCHCK
tCKHL
tCKLH
x1 Period
80
35
35
–
125
–
ns
ns
ns
ns
ns
x1 Low Time
x1 High Time
x1 Fall Time
x1 Rise time
–
5
–
5
CLKOUT Timing
42
43
44
45
46
61
69
70
tCLCL
tCLCH
tCHCL
clkouta Period
20
9
–
–
ns
ns
ns
ns
ns
ms
ns
ns
clkouta Low Time
clkouta High Time
9
–
tCH1CH2 clkouta Rise Time
tCL2CL1 clkouta Fall Time
–
3
–
3
tLOCK
tCICOA
tCICOB
Maximum PLL Lock Time
–
1
x1 to clkouta Skew
x1 to clkoutb Skew
–
15
21
–
a
In nanoseconds.
0ns
20ns
40ns
60ns
80ns
100ns
120ns
clkouta
47
srdy
48
Figure 22. srdy—Synchronous Ready
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