IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 95. Reset and Bus Hold Timing
a
a
No.
Name
Description
Min
Max
Reset and Bus Hold Timing Requirements
5
tCLAV
tCLAZ
ad Address Valid Delay
ad Address Float Delay
0
12
–
15
57
58
tCLCH
10
tRESIN res_n Setup Time
tHVCL hld Setup Time
–
10
–
Reset and Bus Hold Timing Responses
62
63
64
tCLHAV hlda Valid Delay
0
0
0
7
tCHCZ
tCHCV
Command Lines Float Delay
Command Lines Valid Delay (after Float)
12
12
a
In nanoseconds.
0ns
20ns
40ns
71
60ns
80ns
100ns
120ns
140ns
clkouta
clkoutA
sden
sden
72
sclk
sclk
75
77
sdattaa(RX)
sda (RX)
DATA
78
sdata(TX)
sdata(TX)
DATA
Figure 29. Synchronous Serial Interface
IA211110517-02
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