IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 91. Interrupt Acknowledge Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
6.6
2
–
–
General Timing Responses
3
tCHSV
tCLSH
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
tCLAZ
tDXDL
Status Active Delay
Status Inactive Delay
Data Valid Delay
0
10
10
10
–
4
0
7
0
8
Status Hold Time
0
9
ale Active Delay
0
10
–
10
11
12
15
19
20
21
22
23
31
68
ale Width
15
ale Inactive Delay
0
10
–
ad Address Valid to ale Low
ad Address Float Delay
den_n Inactive to dt/r_n Low
tCLCH
0
0
0
0
0
5
0
0
10
–
tCVCTV Control Active Delay 1
tCVDEX den_n Inactive Delay
tCHCTV Control Active Delay 2
10
10
10
–
tLHAV
tCVCTX Control Inactive Delay
tCHAV
clkouta High to a Address Valid
ale High to Address Valid
10
10
a
In nanoseconds.
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