IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
A
clkouta
68
a19–a01-9a0
Invalid Address
5
(IA186ER)
ad15–ad0 (IA186EM),
ad8–ad0 (IA188EM),
(IA188ER)
Invalid Address
ao15–ao8 (IA188EM)
(IA188ER)
9
11
ale
ela
10
n
den_n
19
dt/r_n
22
3
4
n_
s1_n–s0_n
Status
Figure 19. Software Halt Cycle
Table 92. Software Halt Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Responses
3
tCHSV
tCLSH
tCLAV
tCHLH
tLHLL
tCHLL
tDXDL
Status Active Delay
Status Inactive Delay
ad Address Valid Delay
ale Active Delay
0
0
10
10
10
10
–
4
5
0
9
0
10
11
19
22
68
ale Width
15
0
ale Inactive Delay
den_n Inactive to dt/r_n Low
10
–
0
tCHCTV Control Active Delay 2
tCHAV
clkouta High to a Address Valid
0
10
10
0
a
In nanoseconds.
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