IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 94. Ready and Peripheral Timing
a
a
No.
Name
Description
Min
Max
Ready and Peripheral Timing Requirements
47
48
49
50
51
52
53
54
tSRYCL
tCLSRY
tARYCH
tCLARX
srdy Transition Setup Time
srdy Transition Hold Time
ardy Resolution Transition Setup Time
ardy Active Hold Time
10
3
–
–
–
–
–
–
–
–
9
4
tARYCHL ardy Inactive Holding Time
tARYLCL ardy Setup Time
6
9
tINVCH
tINVCL
Peripheral Setup Time
drq Setup Time
10
10
Peripheral Timing Responses
55 tCLTMV Timer Output Delay
0
12
a
In nanoseconds.
0ns
20ns
40ns
60ns
57
80ns
100ns
120ns
140ns
160ns
1x
x1
57
re_sn
res_n
Low for N x1 Cycles
clkouta
Figure 25. Reset 1
0ns
res_nn
20ns
40ns
60ns
80ns
100ns
120ns 140ns
tri-state
160ns
clkoutaA
bhe_n/aden_n,
rfsh_n/aden_n,
2 s6/clkdiv2, uzi_naed/6,isuz_n
(IA186ER)
ad15–ad0 (IA186EM),
tri-state
ao15–ao8 (IA188EM),
(IA188ER)
ad7–ad0 (IA188EM)
(IA188ER)
Figure 26. Reset 2
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