IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
0ns
20ns
9
40ns
60ns
80ns
100ns
120ns
28
140ns
160ns
180ns
KLC0
clkouta
19a-0
Address
a19–a0
11
ale
ela
27
10
26
rd_n
_drn
80
25
27
81
lcs_n
79
82
85
rfhs_
rfsh_n
86
Figure 16. PSRAM Refresh Cycle
Table 89. PSRAM Refresh Cycle
a
a
No.
Name
Comment
Min
Max
General Timing Responses
9
tCHLH
tLHLL
tCHLL
ale Active Delay
ale Width
0
15
0
10
–
10
11
ale Inactive Delay
10
Read/Write Cycle Timing Responses
25
26
27
28
80
81
tCLRL
rd_n Active Delay
rd_n Pulse Width
rd_n Inactive Delay
0
35
0
10
–
tRLRH
tCLRH
tRHLH
tCLCLX
tCLCSL
10
–
rd_n Inactive to ale High
lcs_n Inactive Delay
lcs_n Active Delay
tCLCH -2
0
0
10
10
Refresh Cycle Timing Responses
79
82
85
86
tCHRFD
tCLRF
tRFCY
tLCRF
clkouta High to rfsh_n Valid
clkouta High to rfsh_n Invalid
rfsh_n Cycle Time
0
0
10
10
–
6tCLCL
2tCLCL -1
lcs_n Inactive to rfsh_n Active Delay
–
a
In nanoseconds.
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