fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
beacon frame through port 2. A change of state in RingBeaconState1 causes the rbs1
IRQ in the Switch Event register and a change of state in RingBeaconState2 causes the
rbs2 IRQ in the Switch Event register.
9.2.26 Beacon Timeout Register
Mnemonic
type offset bits 15
R/W 0x70
14
13
0
12
0
11
0
10
0
9
8
7
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
BcnTmo_Lo
BeaconTimeout[15:0]
Power-up Defaults
0
0
0
9
0
8
0
7
0
6
Mnemonic
type offset bits 15
R/W 0x72
14
0
13
0
12
0
11
0
10
0
BcnTmo_Hi
BeaconTimeout[31:16]
Power-up Defaults
0
0
0
0
0
The Beacon Timeout register consists of two 16-bit registers. The timeout value is used
by both the port 1 beacon timeout timer and the port 2 beacon timeout timer. The beacon
timeout timers are 32-bit down counters that count at 50MHz. When the port 1 (or port 2)
beacon timeout timer is enabled through the p1bte ( or p2bte) bit in the Redundancy
Control register, the value from this register is loaded into respective timer and
countdown begins. When a Ring beacon is received on port 1 (or port 2) with the Ring
Supervisor MAC ID register source address, without a CRC error, the respective port’s
beacon timer is reloaded with the beacon timeout value and the countdown is started
again. If the timer reaches zero the bto1 (or bto2) bit in the Switch Event register is set
and the timer is loaded with the value from this register again for next count down. To
prevent spurious interrupts, this register should be changed only when the p1bte and
p2bte bits are reset in the Redundancy Control register.
9.2.27 Port 1 Beacon Receive Timestamp Register
Mnemonic
type offset bits 15
0x74
Power-up Defaults
14
13
12
11
10
9
8
7
6
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0
P1BcnTS_Lo
R
BeaconTimestamp1[15:0]
0
0
0
0
0
0
0
9
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x76
Power-up Defaults
14
0
13
0
12
0
11
0
10
0
P1BcnTS_Hi
R
BeaconTimestamp1[31:16]
0
0
0
0
0
72
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