fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
7.2 TRANSMIT DATA, External MII Interface
An Ethernet packet to be transmitted will be sent to its respective PHY via an MII interface. The
PHY will transmit this data using the MII inputs: px_txc, px_txen, px_txer and px_txd[3:0].
Timing for the TRANSMIT DATA is shown below in Figure 13.
Figure 13 External MII Interface, TRANSMIT DATA
Table 12 TRANSMIT DATA, External MII Interface
Description
Symbol
ttxdval
min max unit
Transmit Data VALID time
Transmit Data HOLD time
Transmit Data Enable VALID time
Transmit Data Valid HOLD time
Transmit Data Error VALID time
Transmit Data Error HOLD time
15
0
ns
ns
ns
ns
ns
ns
ttxdhd
ttxenval
ttcenhd
ttxerval
ttxerhd
15
0
15
0
8 Internal MII Interface
The single internal port, port CPU, of the 3-Port Industrial Ethernet Switch acts as a physical
layer transceivers (PHY) media independent interface (MII). This MII interface is comprised of
16 pins: transmit clock (cpu_txc), transmit enable (cpu_txen), transmit error (cpu_txer), transmit
data (cpu_txd[3:0]), receive clock (cpu_rxc), receive data valid (cpu_rxdv), receive data error
(cpu_rxer), receive data (cpu_rxd[3:0]), collision (cpu_col) and carrier sense (cpu_crs).
However, as the Internal MII Interface always runs at 100MB and Full-Duplex, the output
cpu_col is always low and the output cpu_crs is the same as cpu_rxdv.
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