fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
6 Host Bus Interface
The Host Bus Interface is used to read and/or write the various configuration and data registers
within the fido2100. The Host Bus Interface consists of the following inputs, an 8-bit address bus
(cpu_adrs[8:1]), a chip select (cpu_cs_n), a read select (cpu_rd_n) and a write select (cpu_wr_n),
along with a 16-bit bidirectional data bus (cpu_data[15:0]).
6.1 READ, Host Bus Interface
A READ is accomplished by selecting a register address using input cpu_adrs[8:1], then
asserting both cpu_cs_n and cpu_rd_n inputs for a sufficient time. The contents of the register
READ will be output on cpu_data[15:0]. The input cpu_wr_n must not be asserted during a
READ operation. A typical READ operation, with necessary timing, can be seen below in Figure
10. During the READ operation the timing between cpu_cs_n and cpu_rd_n is not critical,
however the actual READ cycle begins when both signals are asserted low with the last asserted
signal determining the timing. The READ cycle will end when either cpu_cs_n or cpu_rd_n are
de-asserted high. In the timing diagram of Figure 10, timing is shown only from cpu_rd_n for
simplicity.
Figure 10 Host Interface, READ Timing
Table 9 Host Interface, READ Timing
Description
Symbol
tadsu
min max unit
cpu_adrs SETUP time
cpu_adrs HOLD time
cpu_data VALID time
cpu_data HOLD time
cpu_rd_n DEAD time
0
ns
ns
ns
ns
ns
tadhd
tdatval
tdathd
trddt
60
60
0
40
40
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