fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
9 Control and Status Registers
Table 13 below contains a listing of all Control & Status Registers accessible from the Host Bus
Interface. The table includes the address, register name, a register mnemonic and the read/write
status of the register. A detailed explanation of the registers is also included in this section
following the table.
9.1 Register Map
Table 15 Register Map
Address
Function
Mnemonic
R/W
Offset
(cpu_adrs[8:0])
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
Time Sync Control
TS_Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Time Sync IRQ Event
Addend_Low
TS_Event
Addend_Lo
Addend_High
Addend_Hi
Accumulator_Low
Accum_Lo
Accumulator_High
Accum_Hi
SystemTime_Low_Low
SystemTime_Low_High
SystemTime_High_Low
SystemTime_High_High
TargetTime1_Low_Low
TargetTime1_Low_High
TargetTime1_High_Low
TargetTime1_High-High
TargetTime2_Low_Low
TargetTime2_Low_High
TargetTime2_High_Low
TargetTime2_High_High
Event1Snap_Low_Low
SysTime_Lo_Lo
SysTime_Lo_Hi
SysTime_Hi_Lo
SysTime_Hi_Hi
TgtTim1_Lo_Lo
TgtTim1_Lo_Hi
TgtTim1_Hi_Lo
TgtTim1_Hi_Hi
TgtTim2_Lo_Lo
TgtTim2_Lo_Hi
TgtTim2_Hi_Lo
TgtTim2_Hi_Hi
Evnt1_Lo_Lo
46
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