fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
5.4 RESET: Power-On-Reset, Hardware Reset and Software Reset
5.4.1 Power-On-Reset
The fido2100 has an internal power-on-reset (POR) circuit which will provide a reset of the PLL
and the rst bit of the Switch Control Register when vcck power is applied. The POR circuit will
keep the PLL and rst bit in reset until the vcck power has exceeded a 1.2 V threshold. Once the
vcck voltage has exceeded the POR threshold the PLL will then need a minimum time of 60 ns to
lock and provide a stable clock source.
5.4.2 Hardware Reset
There is also a reset input (reset_n) provided for a hardware reset of the fido2100. When reset_n
is asserted low the POR circuit will reset the PLL and the rst bit of the Switch Control Register.
The reset_n input must be asserted low for a minimum of 20 ns in order to assure a reset has
occurred. On a reset, once the reset_n input has been de-asserted high, the PLL will then need a
minimum time of 60 ns to lock and provide a stable clock source. The reset_n input has an
internal pull-up which is intended to prevent a reset if the input is un-driven.
5.4.3 Software Reset
Software reset of the fido2100 is accomplished by writing a '1' to the rst bit of the Switch
Control Register. The rst bit is self-clearing on the next clock. When this bit is set, the control
and status registers return to their default conditions.
5.5 Test Input
The test input (test) should be tied low externally for normal operation. There are no user
selectable tests. The test input has an internal pull-down which is intended to prevent a entering
test mode if the input is un-driven.
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