fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
6.2 WRITE, Host Bus Interface
A WRITE is accomplished by selecting a register address using input cpu_adrs[8:1], placing
data on cpu_data[15:0], and then asserting both cpu_cs_n and cpu_wr_n inputs for a sufficient
time. The data on the cpu_data[15:0] bus will then be written to the selected register. The input
cpu_rd_n must not be asserted during a WRITE operation. A typical WRITE operation, with
necessary timing, can be seen below in Figure 11. During the WRITE operation the timing
between cpu_cs_n and cpu_wr_n is not critical, however the actual WRITE cycle begins when
both signals are asserted low with the last asserted signal determining the timing. The WRITE
cycle will end when either cpu_cs_n or cpu_wr_n are de-asserted high. In the timing diagram of
Figure 11, timing is shown only from cpu_wr_n for simplicity.
Figure 11 Host Interface, WRITE Timing
Table 10 Host Interface, WRITE Timing
Description
Symbol
tadsu
tadhd
tdtsu
tdthd
twr
min max unit
cpu_adrs SETUP time
cpu_adrs HOLD time
cpu_data SETUP time
cpu_data HOLD time
cpu_wr_n WRITE time
cpu_wr_n DEAD time
0
0
ns
ns
ns
ns
ns
ns
0
0
50
40
twrdt
41
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