fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
There are two 64-bit target time registers and comparators that can be used to generate an interrupt to
the host CPU when the system time counter reaches the target time. This feature can be used by
firmware to schedule/coordinate control loops/activities. While both target time registers can be used
by firmware for any purpose, the second target time register has a special capability to generate a pulse
per second signal. The pulse per second signal is required for internal IEEE 1588 compliance testing,
but is not required on shipping products.
There are two additional snapshot registers for two external events. These snapshots can be used to
synchronize system time with an external clock. For example, the event 1 can be used to synchronize
internal IEEE 1588 system time as a slave with a global positioning system (GPS) signal as the master.
Similarly, the event 2 can be used to synchronize internal IEEE 1588 system time as a master with an
external clock in another module in the system as the slave. Both event snapshots have the same
capability/behavior in implementation and they can be used interchangeably.
2.2.2 IEEE 1588 End to End Transparent Clock
The fido2100 implements an integrated IEEE 1588 V2 end to end transparent clock (E2E TC). This is a
single step transparent clock in IEEE 1588 terminology. The supported frame mapping is PTP over
UDP over IPV4 over IEEE 802.3 tagged or untagged frames. The E2E TC uses a non-syntonized free
running timer as a time base. The free running timer runs at 100MHz, but the timestamp circuit uses
both edges of the clock for sampling, and delay computation is suitably adjusted to make it effectively
run at 200MHz, with 5 ns resolution.
In E2E TC mode, whenever an IEEE 1588 V2 Sync or Delay_Req frame is received, a receive
timestamp is triggered on ingress at the timestamp point following the start of frame delimiter. The
frame is parsed to extract the UDP checksum and correction field. When the received frame doesn’t
contain any errors and when the frame is transmitted through a port, a transmit timestamp is triggered
on egress at the timestamp point. The residence time delay is then computed on the fly from the
transmit and receive timestamps. The residence time delay is then added to the correction field in the
frame with the UDP checksum and frame CRC adjusted on the fly.
Without transparent clocks, cascaded switches or boundary clocks will accumulate errors at
exponential rate making time synchronization unstable. With transparent clocks the accumulation of
errors is linear with the number of nodes. The implemented E2E TC has a theoretical worst case error
of +/-15 ns per node assuming 50PPM source crystal oscillator stability.
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