fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
CRC generator and the least significant 11 bits of the resulting CRC is used to index into the 2048 bin
hash table. When the indexed bin in the hash table is set, the frame will be forwarded to the internal
port and the other external port. If not set, the frame will be forwarded only to the other external port.
By default, all 2048 bins of the multicast hash table are set to zero after power up or chip reset, and no
multicast frames will be forwarded to the internal port. Since most devices such as I/O devices don’t
need to receive multicast frames, they don’t need to change this default behavior. Note that the
multicast filter table need not be set for receiving multicast ring frames.
2.7 Statistics Counters
The fido2100 implements statistics counters for the external ports. These counters can be used by
firmware for the media and interface counters of the EtherNet/IP Ethernet Link object (Class Code:
0xF6). Most of these counters are 16 bits wide and to avoid roll over issues, firmware must read these
registers at least once every 200 milliseconds or on demand, to calculate an increase in counter values.
The firmware can then add the increase to firmware maintained 32 bit counters.
Counters are implemented for valid frames received with the group bit set in the destination address,
valid frames received with a unicast destination address, total byte count of valid frames received,
frames received with length greater than 1522 bytes, frames received with alignment error, frames
received with a frame check sequence (CRC) error and frames received with other errors, including
short runt frames less than 64 bytes in length.
Counters are also implemented for valid frames transmitted with the group bit set in the destination
address, valid frames transmitted with a unicast destination address, total byte count of valid frames
transmitted, frames transmitted after exactly one collision, frames transmitted after multiple collisions,
frames dropped due to excessive collisions and frames truncated with error during transmission.
2.8 Buffer Management
The fido2100 implements an efficient packet buffering scheme using on board dual port SRAM
memory. The buffers are 128 bytes in size to minimize memory wastage. Frames longer than 128 bytes
are automatically fragmented to be stored in multiple buffers and reassembled during transmission.
Actual buffer usage depends on a number of factors such as network load, number of frames waiting to
be transmitted at each node at the same time, the number of back to back frames arriving at the
destination node through both external ports at the same time, etc. For some devices such as motion
drives and I/O, buffer usage on any port may never exceed 10% of buffer capacity. For other devices
such as network bridges, buffer usage on any port may be typically less than 50% of buffer capacity
during normal operation. Irrespective of the type of end device, when buffer usage reaches 95% of
buffer capacity on any port under heavily loaded network conditions, flow control will intervene to
reduce buffer usage and will ensure frames are not being dropped.
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