fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
2.1.2 Half Duplex Flow Control and Broadcast/Multicast Storm Prevention
The fido2100 implements back pressure flow control in half duplex mode. When both external ports
are operating in same speed and half duplex mode, and buffer usage on the internal port or other
external port reaches 95% of buffer capacity, back pressure flow control is activated on the first
external port. This continues until the buffer usage on both internal and second external ports reaches
below 85% of buffer capacity. When back pressure flow control is activated on a port, the port will
continue to transmit frames while it has any. If there is no frame to transmit, the frame will keep the
carrier sense signal active by sending the preamble pattern periodically, causing the neighboring node
to back off from transmitting any frames. If speed and duplex modes of external ports are not same,
back pressure will not be activated.
Excessive broadcast frames can overload the CPU of all devices on network, especially IO adapters and
IO blocks, leading to poor performance. To avoid this, the fido2100 implements a broadcast storm
prevention mechanism. When received broadcast data within a 100 millisecond period (1 second at
10Mbps) reaches about 1% of network bandwidth in a port operating at 100Mbps speed, additional
broadcast frames received on that port within that period will be dropped. This process is repeated for
every 100 millisecond period. In well-engineered networks, broadcast storms do not occur during
normal operation and a 1% broadcast storm limit will never be reached.
Similarly every port is also monitored for received non-redundancy (non-DLR/BRP) multicast frames.
When received non-redundancy multicast data within a 10 millisecond period (100 milliseconds at
10Mbps) reaches about 50% of network bandwidth in a port operating at 100Mbps speed, additional
nonredundancy multicast frames received on that port within that period will be dropped. This process
is repeated for every 10 millisecond period. In well-engineered networks, multicast storms do not occur
during normal operation.
2.2 IEEE 1588 V2
2.2.1 IEEE 1588 Hardware Assist for Ordinary Clock
Figure 2 below shows a block diagram of the IEEE 1588 V2 hardware assist that can be used to
implement an IEEE 1588 ordinary master or slave clock on an end device. The MII traffic of the
internal port between the host CPU and the fido2100 is monitored by two independent 1588 frame
detection logic blocks, one for the transmit channel and the other for the receive channel.
Whenever the timestamp point of a passing transmit/receive frame is reached, a snapshot of the system
time counter is saved in a temporary register. When the appropriate 1588 frame type is also detected in
the frame, the snapshot is saved from the temporary register to the transmit/receive snapshot register.
The receive snapshot register contains a sixteen entry FIFO, while the transmit snapshot register is a
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