fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
While transmit and receive frame detection logic operate independently at 25MHz MII clock rates, the
rest of the logic operates at 100MHz clock rate. The addend register and accumulator of frequency
compensated clock are 32-bits wide, while the system time counter is 64-bits wide. The tunable
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precision for frequency compensation is better than 1 part per billion (1x10 ). The procedure for
realizing various nominal system time frequencies is described below.
FreqOscillator is the clocking frequency of the time synchronization
FreqClock is the nominal frequency at which the system time counter is to be incremented.
FreqDivisionRatio = FreqOscillator / FreqClock (This must always be > 1)
FreqCompensationValue = frequency compensation value is the number held in the
addend register, which is added to the accumulator once every 1/FreqOscillator.
The equation for the FreqCompensationValue utilizes the precision of the accumulator and the
FreqDivisionRatio. Since the accumulator is 32 bits, the following equation provides the value for the
Addend register:
32
FreqCompensationValue = 2 / FreqDivisionRatio
The hexadecimal representation of the FreqCompensationValue is the value that is written to the
addend register. The following table gives examples of addend values based on a 100 MHz
FreqOscillator.
Freq-oscillator
100 MHz
FreqClock
83.33 MHz
80 MHz
FreqDivisionRatio FreqCompensationValue
1.2
1.25
1.5
0xD5555555
0xCCCCCCCD
0xAAAAAAAB
100 MHz
100 MHz
66.66 MHz
The synchronization accuracy between the time master and the slave depend on cumulative accuracy of
individual components used in the system. When a time slave is connected directly to the time master,
a synchronization accuracy of less than 50 ns from master is easily possible. This accuracy is
achievable with low cost 50PPM crystal clock oscillators. Turbulent air flow over the crystal oscillator
should be avoided to prevent rapid temperature changes resulting in short term stability errors. Some
PHY devices introduce random delays in transmit and receive paths, which can increase time
synchronization errors significantly. It is recommended that the PHY devices be investigated for such
behavior. Any asymmetry in transmit and receive paths should be accounted properly by firmware to
avoid accumulation of errors. In a cascaded transparent clock configuration between the time master
and the slave, the errors will increase linearly with the number of transparent clocks.
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