fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
single entry register. With the transmit snapshot register, the snapshot will be locked to prevent
overwriting by subsequent frames. The firmware must later clear the lock after it has read the snapshot.
With the receive snapshot register, the firmware should read all snapshots while the FIFO is not empty.
If the FIFO becomes full because the firmware is slow to read it, additional snapshots will not be saved
until the FIFO has a free entry. To distinguish saved snapshots, the received frame sequence identifier
and source port identity are also locked in the FIFO and may be read through appropriate registers
along with the snapshot.
Figure 2 IEEE 1588 Hardware Assist Block Diagram
The supported frame mapping for frame detection logic is PTP over UDP over IPV4 over IEEE 802.3
tagged or untagged frames. The frames detected are based on the master mode bit setting in the time
sync control register. In master mode, Sync frames are time stamped on transmit and Delay_Req
frames are time stamped on receive. In slave mode, Delay_Req frames are time stamped on transmit
and Sync frames are time stamped on receive. In addition, the sub-domain field of frames must match
the subdomain configuration register for the snapshot to be saved.
The addend register, accumulator and system time counter comprise a frequency compensated clock
under firmware control. The accumulator adds the addend register to itself on every incoming clock
from the oscillator and the overflow signal of the accumulator causes the system time counter to
increment. This provides a high precision tunable digital clock whose frequency of operation can be
controlled by firmware through writing suitable values to the addend register.
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