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AM188EM-20VIW 参数 Datasheet PDF下载

AM188EM-20VIW图片预览
型号: AM188EM-20VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 146 页 / 1574 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EM/IA188EM  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
February 25, 2011  
2.2.33 s2_ns0_nBus Cycle Status (synchronous outputs with tristate)  
These three signals inform the system of the type of bus cycle in progress. The s2_n may be  
used to indicate whether the current access is to memory or I/O, and s1_n may be used to  
indicate whether data is being transmitted or received. These signals are tristated during bus  
hold and hold acknowledge. The coding for these pins is presented in Table 10.  
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n  
s2_n s1_n s0_n Bus Cycle  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt acknowledge  
Read data from I/O  
Write data to I/O  
Halt  
Instruction fetch  
Read data from memory  
Write data to memory  
None (passive)  
2.2.34 s6/clkdiv2_n/pio29Bus Cycle Status Bit 6 (synchronous output)/Clock Divide  
by 2 (input with internal pull-up)  
The s6 signal is high during the second and remaining cycle periods (i.e., t2 t4), indicating that a  
DMA-initiated bus cycle is underway. The s6 is tristated during bus hold or reset.  
If the clkdiv2_n signal is held low during power-on-reset, the microcontroller enters clock  
divide-by-2 mode. In this mode, the PLL is disabled and the processor receives the external  
clock divided by 2. Sampling of this pin occurs on the rising edge of res_n.  
Note: If this pin is used as pio29 and configured as an input, care should be  
taken that it is not driven low during POR.  
Because this pin has an internal pull-up, it is not necessary to drive the pin high even though it  
defaults to an input PIO.  
2.2.35 sclkSerial Clock (synchronous outputs with tristate)  
Because this pin provides a slave device with a synchronous serial clock it permits  
synchronization of the transmit and receive data exchanges between the slave and the  
microcontroller. The sclk is the result of dividing the internal clock by 2, 4, 8, or 16, depending  
on the contents of the Synchronous Serial Control (SSC) register Bits [54]. Accessing either  
the SSR or SSD registers activates the sclk for eight cycles. When sclk is not active, the  
microcontroller hold is high.  
®
IA211050831-19  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.Innovasic.com  
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