IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
The nmi is not involved in the priority resolution process that deals with the maskable interrupts
and does not have an associated interrupt flag. This allows for a new nmi request to interrupt an
nmi service routine that is already underway. When an interrupt is taken by the processor the
interrupt flag IF is cleared, disabling the maskable interrupts. If the maskable interrupts are
reenabled during the nmi service routine (e.g., by use of STI instruction), the priority resolution
of maskable interrupts will be unaffected by the servicing of the non-maskable interrupt (NMI).
Note: For this reason, it is strongly recommended that the NMI interrupt
service routine does not enable the maskable interrupts.
2.2.25 pcs3_n–pcs0_n (pio19–pio16)—Peripheral Chip Selects 3–0 (synchronous
outputs)
The pcs3_n–pcs0_n pins provide an indication that a memory access is underway for the
corresponding region of the peripheral memory block (I/O or memory address space). The base
address of the peripheral memory block is programmable. The pins are held high during both
bus hold and reset. These outputs are asserted with the ad address bus over a 256-byte range
each.
2.2.26 pcs5_n/a1—Peripheral Chip Select 5 (synchronous output)/Latched Address Bit 1
(synchronous output)
The pcs5_n signal provides an indication that a memory access is underway for the sixth region
of the peripheral memory block (I/O or memory address space). The base address of the
peripheral memory block is programmable. The pcs5_n is held high during both bus hold and
reset. This output is asserted with the ad address bus over a 256-byte range.
This a1 pin provides an internally latched address bit 1 to the system when the EX bit (Bit [7]) in
the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched value
during a bus hold.
2.2.27 pcs6_n/a2—Peripheral Chip Select 6 (synchronous output)/latched Address Bit 2
(synchronous output)
The pcs6_n signal provides an indication that a memory access is underway for the seventh
region of the peripheral memory block (I/O or memory address space). The base address of the
peripheral memory block is programmable. The pcs6_n is held high during both bus hold and
reset. This output is asserted with the ad address bus over a 256-byte range.
The a2 pin provides an internally latched address Bit [2] to the system when the EX bit (Bit [7])
in the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched value
during a bus hold.
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