IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
2.2.28 pio31–pio0—Programmable I/O Pins (asynchronous input/output open-drain)
There are 32 individually programmable I/O pins provided (see Table 15, Default Status of PIO
Pins at Reset).
2.2.29 rd_n—Read strobe (synchronous output with tristate)
The rd_n pin provides an indication to the system that a memory or I/O read cycle is underway.
It will not to be asserted before the ad bus is floated during the address to data transition. The
rd_n is tristated during bus hold.
2.2.30 res_n—Reset (asynchronous level-sensitive input)
The res_n pin forces a reset on the microcontroller. Its Schmitt trigger allows POR generation
via an RC network. When this signal is asserted, the microcontroller immediately terminates its
present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h.
The res_n must be asserted for at least 1 ms. Because it is synchronized internally it may be
asserted asynchronously to clkouta. Furthermore, vcc must be within specification and clkouta
must be stable for more than four of its clock periods for the period that res_n is asserted.
The microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of
res_n.
2.2.31 rfsh2_n/aden_n (IA188EM)—Refresh 2 (synchronous output with tristate)/Address
Enable (input with internal pull-up)
The rfsh2_n indicates that a DRAM refresh cycle is being performed when it is asserted low.
However, this is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead.
If the aden_n pin is held high during POR, the ad bus (ao15–ao8 and ad7–ad0 for the IA188EM)
is controlled during the address portion of the lcs and ucs bus cycles by the DA bit (Bit [7]) in
the lcs and ucs registers. If the DA bit is 1, the address is accessed on the a19–a0 pins, reducing
power consumption. The weak pull-up on this pin obviates the necessity of an external pull-up.
If the aden_n pin is held low during POR, the ad bus is used for both addresses and data without
regard for the setting of the DA bits. The rfsh2_n/aden_n is sampled one crystal clock cycle
after the rising edge of res_n and is tristated during bus holds and ONCE mode.
2.2.32 rxd/pio28—Receive Data (asynchronous input)
This signal connects asynchronous serial receive data from the system to the asynchronous serial
port.
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