IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bit [5–3]—Reserved. Set to 1.
Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, an
external ready is required. The value of these bits determines the number of wait states
inserted.
Bits [1–0]—R [1–0] Wait-State Value → The value of these bits determines the number
of wait states inserted into an access to the lcs_n memory area. This number ranges from
0 to 3 (R1–R0 = 00b to 11b).
5.1.21 SP0BAUD (088h)
Serial Port BAUD Rate Divisor Registers.
5.1.22 SP1BAUD (018h)
Two baud-rate divisor registers, one for each port, allow the two ports to operate at different
baud rates. The value in these registers determines the number of internal processor cycles in
one phase (one half period) of the 16x serial clock.
The contents of these registers must be adjusted to reflect the new processor clock frequency if
power-save mode is in effect.
The baud rate divisor may be calculated from:
BAUDDIV = (Processor Frequency/(16 x baud rate))
(Equation 2)
By setting the BAUDDIV to 0001h, the maximum baud rate of 1/16 of the internal processor
frequency clock is set. This provides a baud rate of 2500 Kbytes at 40 MHz. If the BAUDDIV
is set to zero, transmission or reception of data does not occur. The baud rate tolerance is +3.0%
and −2.5% with respect to the actual serial port baud rate, not the target baud rate (see Table 37).
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