IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Address Ranges of pcs Chip Selects
Range
pcs_n Line
pcs0_n
pcs1_n
pcs2_n
pcs3_n
Reserved
pcs5_n
pcs6_n
Low
High
Base Address
Base Address + 256
Base Address + 512
Base Address + 768
NA
Base Address + 255
Base Address + 511
Base Address + 767
Base Address + 1023
NA
Base Address + 1280 Base Address
Base Address + 1536 Base Address
Bits [6–4]—Reserved. Set to 1.
Bit [3]—R [3] → Wait State Value. See pcs3_n–pcs0_n Wait-State Encoding shown
below.
pcs3_n–pcs0_n Wait-State Encoding
R3 R1 R0 Wait States
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
5
7
9
15
Bit [2]—R [2] → Ready Mode. When set to 1, external ready is ignored. When 0, it is
required. In each case the number of wait states is determined according to the
pcs3_n–pcs0_n Wait-State Encoding shown above.
Bits [1–0]—R [1–0] → Wait-State Value (see pcs3_n–pcs0_n Wait-State Encoding shown
above). The pcs6_n–pcs5_n and pcs3_n–pcs0_n pins are multiplexed with the PIO pins.
For them to function as chip selects, the PIO mode and direction settings for these pins
must be set to 0 for normal operation.
5.1.19 LMCS (0a2h)
The Low-Memory Chip Select (LMCS) Register configures the Low Memory Chip Select
provided to facilitate access to the interrupt vector table located at 00000h or the bottom of
memory. The lcs_n pin is not active at reset.
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